25 –26 27 Binary Adder –32 Arithmetic Logic Unit (ALU) 32 –35 36 Assignment 1 d = 5 + e (S2) A processor register Each of these instructions has the following format. The only data memory references made by the program are those to array ARR, The total size of the tags in the cache directory is. It is our sincere effort to help you. A processor has 40 distinct instructions and 24 general purpose registers. The cache is initially empty and no pre-fetching is done. Consider a RISC machine where each instruction is exactly 4 bytes long. P3: Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns. Assume that the memory is word addressable. The time required to perform one refresh operation on all the cells in the memory unit is. Consider the following program segment. What are the tag and cache line address (in hex) for main memory address (E201F)16? /* Initialize array ARR to 0.0 * / Further the Offset is always with respect to the address of the next instruction in the program sequence. For this application, the miss rate of L1 cache is 0.1; the L2 cache experiences, on average, 7 misses per 1000 instructions. The number of bits in the tag field of an address is, The minimum number of D flip—flops needed to design a mod-258 counter is. Which of the following is/are true of the auto-increment addressing mode? The size of double is 8Bytes. d = a + b The following code is to run on a pipelined processor with one branch delay slot: How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? I4 : STORE Memory [R4] ← R1 The number of clock cycles required for completion of execution of the sequence of instructions is ______. The number of clock cycles taken for the execution of the above sequence of instructions is _________. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipelined delay, the clock speed is reduced to 2 gigahertz. The stack pointer(SP) points to the top element of the stack. I. L1 must be a write-through cache A processor can support a maximum memory of 4GB, where the memory is word-addressable (a word consists of two bytes). On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory. The address of a sector is given as a triple 〈c,h,s〉, where c is the cylinder number, h is the surface number and s is the sector number. Consider a two-level cache hierarchy with L1 and L2 caches. When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. Machine Instructions. The DMA controller requires 20 clock cycles for initialization and other overheads. P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns. I. A certain processor deploys a single-level cache. Here R1, R2 and R3 are the general purpose registers. Which one of the following memory block will NOT be in cache if LRU replacement policy is used? The current value of SP is (016E)16. The speed up achieved in this pipelined processor is _____. How many data cache misses will occur in total? The test contains all the questions related to Computer Organization and Architecture. In execution of a program, 60% of memory read are for instruction fetch and 40% are for memory operand fetch. Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The miss penalty from the L2 cache to main memory is 18 clock cycles. The associativity of L2 must be greater than that of L1 It is also estimated that 70% of memory requests are for read and remaining are for write. The lines of a set are placed in sequence one after another. After the execution of this program, the content of memory location 2010 is: Assume that the memory is byte addressable and the word size is 32 bits. Computer Organization & Architecture Notes, GATE Computer Science Notes, GATE Topic Wise Notes, Ankur Gupta GATE Notes, GATE Handwritten Notes, Topper Notes III. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation The average read access time in nanoseconds (up to 2 decimal place) is ____________ . The number of bits available for the immediate operand field is __________. (S1) A memory operand The number of bits in the TAG, LINE and WORD fields are respectively: Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. int i, j ; Which one of the following statements is correct in this context? If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected? Consider a machine with a byte addressable main memory of 220 bytes, block size of 16 bytes and a direct mapped cache having 212 cache lines. Consider the following instruction sequence. The read access time of main memory is 90 nanoseconds. A main memory unit with a capacity of 4 megabytes is built using 1M×1-bit DRAM chips.Each DRAM chip has 1K rows of cells with 1K cells in each row. Consider a hypothetical processor with an instruction of type LW R1 , 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. 18 Free videos ₹4,500.00. The capacity of the disk pack and the number of bits required to specify a particular sector in the disk are respectively: Consider a pipelined processor with the following four stages: IF: Instruction Fetch II. Consider the following code sequence having five instructions I1 to I5. We have also provided number of questions asked since 2007 and average weightage for each subject. An application incurs 1.4 memory accesses per instruction on average. These notes will be helpful in preparing for semester exams and competitive exams like GATE, NET and PSU's. The representation of X in hexadecimal notation is, Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. Consider a machine with a byte addressable main memory of 216 bytes. The cache block size is 16 bytes. When an application is executing on this 6-stage pipeline, the speedup achieved with respect to non-pipelined execution if 25% of the instructions incur 2 pipeline stall cycles is ______________________. Questions on Machine Instructions and Programs. The word length is 32 bits. In Computer Science Engineering (CSE), Computer Organization and Architecture is a set of rules that describe the capabilities and programming model of a computer. e = c + d GATE CS Topic wise Questions Computer Organization and Architecture Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory? The amount of increment depends on the size of the data item accessed, Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor? The instructi ons produce result only in a register. How many 32K × 1 RAM chips are needed to provide a memory capacity of 256 K-bytes? The average memory access time (in nanoseconds) in executing the sequence of instructions is __________. Operand forwarding is used in the pipelined processor. The list ratio for read access is only 80%. Generally, we tend to think computer organization and computer architecture as same but there is slight difference. 2020 © GATE-Exam.in | Complete Solution for GATE, Computer Science and Information Technology, Machine instructions and addressing modes, Memory Hierarchy: Cache, Main Memory and Secondary Storage, Load the starting address of the subroutine in. Computer Organization. If a program has 100 instructions, the amount of memory (in bytes) consumed by the program text is __________ . if (x > a) { (C) includes many processing units under the supervision of a common control unit (D) none of the above. The processor needs to transfer a file of 29, 154 kilobytes from disk to main memory. The maximum number of stores (of one word each) that can be initiated in 1 millisecond is ____________. Computer system architecture by M. Morris Mano.Computer architecture by Briggs. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. The content of each of the memory locations from 2000 to 2010 is 100.                                 ADD R7, R5, R6 Function locals and parameters 1 More than one word are put in one cache block to (A) Exploit the temporal locality of reference in a program (B) Exploit the spatial locality of reference in a program (C) Reduce the miss penalty (D) None of the above SOLUTION I. This Test will cover complete Computer Organization and Architecture with very important questions, starting off from basics to advanced level. Register renaming can eliminate all register carried WAR hazards All the numbers are in decimal. The number of bits for the TAG field is _____. It must be a trap instruction A stack in the main memory is implemented from memory location (0100)16 and it grows upward. e = b + f A program to be run on this machine begins as follows: 1 Computer Architecture Computer Organization 1 1 Computer Design –4 Positional Numbering Systems 4 –8 Binary Data Representation 8 –12 12 Hamming Codes –15 Booth’s Algorithm 15 –25 CPU Design . 2. Which of the characteristics above are used in the design of a, A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M × 4-bit DRAM chips. The throughput increase of the pipeline is___________ percent. It consist of approx 8-10 marks questions every year in GATE Exam. These video classes have been developed based on the latest GATE syllabus and will be useful for undergraduate students of Computer Science and Information Technology as well as those preparing for GATE exams. Computer Architecture and Organisation Q No: 48 The access time of cache memory is 15 ns and main memory is 100 ns. An access sequence of cache block addresses is of length N and contains n unique block addresses.The number of unique block addresses between two consecutive acceses to the same block address is bounded above by k. What is the miss ratio if the access sequence is passed through a cache of  associativity A ≥ k exercising least-recently-used replacement policy? Get the notes of all important topics of Computer Organization & Architecture subject. 1 Valid bit Ideal way to study CAO would be to go through syllabus and recommended books then solving previous year questions and questions at the end of the chapter in the book. e = c + a; To service a cache miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode(IF), (2) Operand Fetch (OF), (3) Perform Operation(PO) and (4) Write back the result (WB). An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies 1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns, respectively (ns stands for nanoseconds). The minimum average latency (MAL) is _____. I. Bypassing can handle all RAW hazards The load-store instructions take two clock cycles to execute. Memory ← MBR Consider two processors p1 and p2 executing the same instruction set. The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. The miss rate of L1 and L2 respectively are: The read access times and the hit ratio for different caches in a memory hierachy are as given below. Consider the sequence of machine instructions given below. The processor generates 32-bit addresses.     d = d * d; A float type variable X is assigned the decimal value of -14.25. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time. To gain in terms of frequency, the designers have decided to split the ID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns. A hard disk has 63 sectors per track, 10 platters each with 2 recording surfaces and 1000 cylinders. GATE 2019 CSE syllabus contains Engineering mathematics, Digital Logic, Computer Organization and Architecture, Programming and Data Structures, Algorithms, Theory of Computation, Compiler Design, Operating System, Databases, Computer Networks, General Aptitude. P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns. The first tage(with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. Filed Under: CO & Architecture, Subjects Tagged With: computer architecture, computer organization, gate-material, gatecse discussion Primary Sidebar Search this website COMPUTER ORGANIZATION - Logic gates, Boolean Algebra, Combinational Circuits 1. Computer Organization and Architecture GATE (Graduate Aptitude Test in Engineering) Entrance exams CSE Computer Science and Information Technology Engineering Computer Organization and Architecture GATE Exam CS Computer Science and Information Technology - Objective type Online Test Questions and Answers with Solution, Explanation, Solved Problems
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